Among those devices with a large-scale transmission circuit, image displays are known in which liquid crystal devices, EL (electroluminescence) devices, LEDs (light-emitting diodes), or the like are arranged in a matrix. An example of such a matrix-type image display is shown in FIG. 28 as a liquid crystal display 101 constituted by a display unit 102 including pixels PIXs arranged in a matrix and a data signal line drive circuit 103 and a scan signal line drive circuit 104 which drive the pixels PIXs. A control circuit 105 produces a video signal DAT indicative of the display state of each pixel PIX, and an image is displayed based on the video signal DAT. A brief explanation is now given about how the display 101 works. In the data signal line drive circuit 103, a shift register sequentially transfers pulses on a signal line Sn to a signal line Sn+1 in synchronism with a timing signal, such as a clock signal SCK. From the transferred pulses are produced sampling pulses. The sampling unit 103b acquires the incoming video signal DAT in synchronism with the sampling pulses and writes the acquired signal to data signal lines SD. Meanwhile, in the scan signal line drive circuit 104, a shift register sequentially transfers pulses on a scan signal line GLn to a scan signal line GLn+1 in synchronism with a timing signal, such as a clock signal GCK. From the transferred pulses are produced gate pulses for selecting the scan signal line GLn. The opening/closing of the switching elements in the pixels PIXs is controlled using the gate pulses, to write the video signals (data) written to the data signal lines SD to the pixels PIXs and sustain the data written to the pixels PIXs.
In recent years, a technology is in the spotlight which is capable of integrally fabricating a pixel array and its drive circuits controlling the display on a single substrate for various purposes, including miniaturization of the liquid crystal display, enhancement of its resolution, and reduction in its packaging costs. To build a currently popular transmissive liquid crystal display with integrated drive circuits, a transparent substrate must be used. Therefore in many cases, silicon thin film transistors made of polysilicon, which can be fabricated on a substrate made of quarts or other glasses, are used as active elements.
The silicon thin film transistor made of polysilicon (hereinafter, “polysilicon TFT”) has a mobility of about 10-100 cm2/V·s and a threshold value in a range of +1V to +4V when built as an N type and −1V to −4V when built as a P type. For the circuit to operate, the source voltage and the input logic amplitude must be sufficiently high compared to TFT's threshold values. Therefore a voltage of 10 V to 12 V is necessary for a polysilicon-TFT-based circuit to operate.
Incidentally, liquid crystal displays are used as monitors in PDAs (Personal Digital Assistants), mobile telephones, and other mobile information devices and for desktop personal computers. These machines are built around ICs and LSI circuits made of monocrystalline silicon and operate on signal voltages as high as 3 V to 5 V. A conventionally liquid crystal panel was provided with a built-in level shifter to raise the low-amplitude logic input control signal from 3 V to about 12 V to address the problem. This solution is disclosed in, for example, Tokukaihei 11-272240/1999 (Japanese Laid-open Patent Application No. 11-272240, published on Oct. 8, 1999) and U.S. Pat. No. 6,081,131 (Date of Patent: Jun. 27, 2000). According to the disclosed technique, a level shifter is provided as shown in FIG. 29, so that signals pass through the level shifter before being fed to the data signal line drive circuit 103 and the scan signal line drive circuit 104. The level shifter shifts the level of the incoming low-amplitude logic control signal to produce an output to those shift registers in the drive circuits.
The technique has setbacks: the shift registers are clocked to a high-amplitude logic signal and in addition, the high-amplitude logic signal must travel a distance substantially as long as the data signal line drive circuit 103.
Now, we calculate how large a load capacitance the clock wire for a shift register has. FIG. 30 shows a typical shift register constituted by D-type flip flops. Clock wires (CK and CKB) are connected to each stage in the shift register. In each stage, both clock wires are connected to two transistors at their gates, a configuration providing a load gate capacitance.
The wires themselves form capacitive coupling with a base, and the capacitance of a wire is given by the following expression:
                                                                        C                wire                            =                                                C                  plate                                +                                  C                  fringe                                                                                                        =                                                                                          ε                      ox                                        ⁡                                          (                                              W                        -                                                  T                          /                          2                                                                    )                                                        ⁢                                      L                    /                    H                                                  +                                                                            ε                      ox                                        ·                    2                                    ⁢                  π                  ⁢                                                                          ⁢                                      L                    /                                          ln                      ⁡                                              [                                                  1                          +                                                      2                            ⁢                                                                                          H                                ⁡                                                                  (                                                                      1                                    +                                                                                                                  (                                                                                  1                                          +                                                                                      T                                            /                                            H                                                                                                                          )                                                                                                                    1                                        /                                        2                                                                                                                                              )                                                                                            /                              T                                                                                                      ]                                                                                                                                                                    =                                                ε                  ox                                ⁢                                  {                                                                                    (                                                  W                          -                                                      T                            /                            2                                                                          )                                            /                      H                                        +                                          2                      ⁢                                              π                        /                                                  ln                          ⁡                                                      [                                                          1                              +                                                              2                                ⁢                                                                                                      H                                    ⁡                                                                          (                                                                              1                                        +                                                                                                                              (                                                                                          1                                              +                                                                                              T                                                /                                                H                                                                                                                                      )                                                                                                                                1                                            /                                            2                                                                                                                                                              )                                                                                                        /                                  T                                                                                                                      ]                                                                                                                                }                                ⁢                L                                                                        (        1        )            where Cwire is the total capacitance of the wire, Cplate is the capacitance of the wire assuming that the wire is parallel to base plates, and Cfringe is the capacitance due to fringe effect of the wire. The expression is derived using an equivalence model shown in FIGS. 31(a), 31(b) (Basics of MOS Integrated Circuit written and edited by HARA Hisashi, published by Kindai Kagakusha (Modern Science Publishing)) in which the effect of the fringe capacitance Cfringe is replaced with a column wire. In the equations and the figure, W, L, and T are respectively the width, length, and thickness of the wire, and H and εox are respectively the thickness and dielectric constant of a field oxidation film. As would be clearly understood from the expression, the wire capacitance increases in direct proportion to the wire length L. Besides this, adjacent wires form capacitive coupling between them, and its effect is also in direct proportion to the wire length L.
In short, the load capacitance of the clock wire increases in direct proportion to the number of stages in the shift register and also to the length of the wire.
Meanwhile, provided that there is no static current consumption, the electric power consumption in signal transmission is given as the following expression:P=CLfV2  (2)where P is the electric power consumption, CL the load capacitance, f the operating frequency, and V operating voltage.
Expressions (1), (2) show that the electric power consumption increases in direct proportion to the distance that a signal travels in a wire having a load and also to the square of the amplitude of the logic signal. Therefore, in the aforementioned conventional example in which a low-amplitude logic input control signal is stepped up by a level shifter to produce outputs to the data signal line drive circuit and the scan signal line drive circuit, large electric power consumption occurs in the clock wire. The distribution of high-amplitude logic, high-frequency clock wires across the entire substrate will likely cause undesirable radiation.
For comparison, FIG. 32 shows a part of a signal line drive circuit or a scan line drive circuit in a liquid crystal display prepared using the polysilicon mentioned in Tokukaihei 6-95073 (published on Apr. 8, 1994). A shift register 201 operates with a low-amplitude logic signal. The output of the shift register 201 is stepped up by the level shifter 202 to a high-amplitude logic signal which is used in driving liquid crystal. The document asserts that the configuration allows the clock wire to carry only the low-amplitude logic signal and thus restrains electric power consumption and unnecessary radiation. However, in this prior art, the shift register is composed of polysilicon, which is inferior to the aforementioned monocrystalline silicon both in mobility and threshold value, and driven by low-amplitude logic signals. The shift register therefore has a smaller drive voltage margin and will likely result in a higher rate of malfunctions and a less drive speed than in a case where a high-amplitude logic signal is used.
In contrast, Tokukai 2000-75842 (Japanese Laid-open Patent Application 2000-75842, published on Mar. 14, 2000) and Tokukai 2000-163003 (Japanese Laid-open Patent Application 2000-163003, published on Jun. 16, 2000) are summarized as follows. FIG. 33 is a diagram showing a typical shift register constituted by D-type flip flops. The shift register 301 is made up of D-type flip flops 302a, 302b, . . . which are connected in series. According to Tokukai 2000-75842 and Tokukai 2000-163003, as shown in FIG. 34, a logic signal transmitted with low amplitude on the clock wire is stepped up by level shifters 303a, 303b, . . . distributed in respective stages to produce a high-amplitude logic signal which is fed to the shift register. Electric power consumption in the clock wire, which is a transmission system, is thus reduced. Further, the shift register operating with a high-amplitude logic signal can improve the operating margin and drive speed of the shift register, which was an issue with Tokukaihei 6-95073.
However, in the shift registers, disclosed in Tokukai 2000-75842 and Tokukai 2000-163003, which include a built-in level shifter coupled to the clock signal input of each stage, the clock signal is a logic signal with a low amplitude from an external control circuit to a level shifter in the shift register in a signal line drive circuit or a scan line drive circuit in a liquid crystal panel. Therefore, if logic operations using a signal from the control circuit are required before the signal line drive circuit or scan line drive circuit in the liquid crystal panel, the use of this low-amplitude logic signal causes practical problems, that is, the aforementioned malfunctions due to a smaller voltage operating margin for operations and slow operating speed. For example, to reduce the drive frequency of the shift register in the data signal line drive circuit, a multiphase shift register may be used, in which event the clock signal from an external circuit must be subjected to a dividing process. As mentioned earlier, the characteristics of polysilicon TFTs are insufficient to carry out these logic operations, and a high-amplitude logic signal is required.
In this manner, in a device using polysilicon TFTs, a high-amplitude logic signal is necessary to a signal operating unit, while a low-amplitude logic signal is demanded in long and large-scale transmission systems to cut electric power consumption and undesirable radiation.